functional block diagram a integrated dual codec and dsp microcomputer preliminary technical data AD73422-40K features single (+2.7v to +5.5v) supply operation codec dual 16-bit a/d converter dual 16-bit d/a converter programmable input/output sample rates 75 db adc snr 70 db dac snr 64 ks/s maximum sample rate -90 db crosstalk low group delay (25 m m m m m s typ per channel) programmable input/output gain flexible serial port which allows extra ad733xx devices to be cascaded on-chip reference dsp microcomputer 30 ns instruction cycle time from 16.67 mhz crystal @ 5.0 volts 33 mips sustained performance single-cycle instruction execution single-cycle context switch 3-bus architecture allows dual operand fetches in every instruction cycle multifunction instructions power-down mode featuring low cmos standby power dissipation with 100 cycle recovery from power-down condition low power dissipation in idle mode draft prelim b1 04/98 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. ice-port is a trademark of analog devices, inc. ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 general description the AD73422-40K combines an ad73322 dual analog front end (afe) with an adsp-218x dsp core in a single device. it is suitable for a variety of applications in the speech and tele- phony area including low bit rate, high quality compression, speech enhancement, recognition and synthesis. the low group delay characteristic of the part makes it suitable for single or multi-channel active control applications.. the AD73422-40K features a dual 16-bit linear codec with programmable analog i/ o gain, sample rates and serial transfer rates. the adsp-218x features the adsp-2100 family base architec- ture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities, and on-chip program and data memory. it is optimized for digital signal processing (dsp) and other high speed numeric processing applications. the AD73422-40K features 40k bytes of on-chip dsp memory configured as 8k words (24-bit) of program ram, and 8k words (16-bit) of data ram. power down circuitry is also provided to meet the low power needs of battery operated por- table equipment. the AD73422-40K is available in a 119-ball plastic ball grid array (pbga) package. applications general purpose analog i/o speech processing cordless and personal communications telephony wireless local loop active control of sound & vibration data communications serial ports memory flags programmable i/o byte dma controller program memory data memory external address bus external data bus dma bus internal dma port timer sport 1 sport 0 adsp-2100 base architecture shifter mac alu arithmetic units powerdown control program sequencer dag 0 dag 1 data address generators program memory program memory address address data memory address data memory address program memory data program memory data data memory data data memory data serial i/o port sigma delta adc sigma delta adc sigma delta dac sigma delta dac reference analog f ront end ad73422 block diagram
draft prelim b 10/97 AD73422-40K C2C serial ports memory flags programmable i/o byte dma controller program memory data memory external address bus external data bus dma bus internal dma port timer sport 1 sport 0 adsp-2100 base architecture shifter mac alu arithmetic units powerdown control program sequencer dag 0 dag 1 data address generators program memory program memory address address data memory address data memory address program memory data program memory data data memory data data memory data serial i/o port sigma delta adc sigma delta adc sigma delta dac sigma delta dac reference analog f ront end ad73422 block diagram figure 1. AD73422-40K block diagram
preliminary technical data AD73422-40K C3C draft prelim b 10/97 connections on plastic bga the AD73422-40K is packaged in a 119-ball pbga. in order to facilitate good layout practice by isolating the digital and mixed-signal sections of the device, the ball-out has been con- figured according to figure 1. the main section is taken up with dsp connections while the next two sections provide con- nectivity to the codec digital and analog sections. a b c d e f g h j k l m n p r t u a b c d e f g h j k l m n p r t u 1234567 1234567 dsp codec digital codec analog figure 1. pbga connectivity
draft prelim b 10/97 AD73422-40K C4C a b c d e f g h j k l m n p r t u a b c d e f g h j k l m n p r t u 1234567 1234567 pbga ball configurations pbga ball pbga ball pbga ball pbga ball number name number name number name number name a1 irqe/pf4 e3 rfs0 j5 d22 n7 d13 a2 dms e4 a3/iad2 j6 d21 p1 ebr a3 vdd e5 a2/iad1 j7 d20 p2 d0/iad13 a4 clkin e6 a1/iad0 k1 elout p3 dvdd a5 a11/iad10 e7 a0 k2 elin p4 dgnd a6 a7/iad6 f1 dr0 k3 eint p5 resetc a7 a4/iad3 f2 sclk0 k4 d19 p6 sclk b1 irql0/pf5 f3 dt1 k5 d18 p7 mclk b2 pms f4 pwdack k6 d17 r1 sdo b3 wr f5 bgh k7 d16 r2 sdofs b4 xtal f6 pf0[mode a] l1 bg r3 sdifs b5 a12/iad11 f7 pf1[mode b] l2 d3/ iack r4 sdi b6 a8/iad7 g1 tfs1 l3 d5/ial r5 se b7 a5/iad4 g2 rfs1 l4 d8 r6 refcap c1 irql1/pf6 g3 dr1 l5 d9 r7 refout c2 ioms g4 gnd l6 d12 t1 vfbp1 c3 rd g5 pwd l7 d15 t2 vinp1 c4 vdd g6 vdd m1 ebg t3 vfbn1 c5 a13/iad12 g7 pf2[mode c] m2 d2/iad15 t4 vinn1 c6 a9/iad8 h1 sclk1 m3 d4/ is t5 vfbn2 c7 gnd h2 ereset m4 d7/ iwr t6 vinn2 d1 irq2/pf7 h3 reset m5 vdd t7 vfbp2 d2 cms h4 pf3 m6 d11 u1 agnd d3 bms h5 fl0 m7 d14 u2 avdd d4 clkout h6 fl1 n1 br u3 voutp2 d5 gnd h7 fl2 n2 d1/iad14 u4 voutn2 d6 d10/iad9 j1 ems n3 vdd u5 voutp1 d7 a6/iad5 j2 ee n4 d6/ ird u6 voutn1 e1 dt0 j3 eclk n5 gnd u7 vinp2 e2 tfs0 j4 d23 n6 d10
preliminary technical data AD73422-40K C5C draft prelim b 10/97 20.32 1.27 3.19 ref 0.84 ref 1.27 a b c d g h j k l m n p r t u e f 1 2 3 4 5 6 7 a1 21.80 22.00 13.80 14.20 7.62 1.85 2.27 0.50 0.70 0.85 0.95 119-pin plastic ball grid array (b-119) outline dim ensions (dimensions shown in mm) 0.60 0.90 0.56 ref top view bottom view
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